Manufacturing process for annealed wafer and annealed wafer
US7081422B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2001 |
| Grant date | Jul 25, 2006 |
| Priority date | — |
| Expiry date | Nov 6, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3225
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There are provided a heat-treating method capable of suppressing generation of slip in a CZ silicon single crystal wafer having a diameter of mainly 300 mm or more even under high temperature heat treatment to annihilate grown-in defects in the vicinity of a surface of the wafer, and an annealed wafer having a DZ layer in a surface layer of the wafer and oxide precipitates in the bulk thereof at a high density which exert a high gettering effect. First heat treatment of a silicon single crystal wafer manufactured from a silicon single crystal ingot pulled by means of a Czochralski method is performed at a temperature in the range of 600 to 1100° C. to form oxide precipitates in the bulk of the wafer, and thereafter, second heat treatment is performed at a temperature in the range of 1150 to 1300° C.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.