Method for forming an SOI substrate, vertical transistor and memory cell with vertical transistor

US7084043B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Albert Birner · Regensburg, DE
• Steffen Breuer · Heiddorf, DE
• Matthias Goldbach · Dresden, DE
• Joern Luetzen · Dresden, DE
• Dirk Schumann · Lübbenau/Spreewald - Lubnjow/Błota, DE

Key dates

• Filing date: Mar 5, 2004
• Grant date: Aug 1, 2006
• Expiry date: Jan 13, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/0385

Abstract

A method for producing a silicon-on-insulator layer structure on a silicon surface with any desired geometry can locally produce the silicon-on-insulator structure. The method includes formation of mesopores in the silicon surface region, oxidation of the mesopore surface to form silicon oxide and rib regions from silicon in single-crystal form; and execution of a selective epitaxy process that that silicon grows on the uncovered rib regions, selectively with respect to the silicon oxide regions. Rib regions remain in place between adjacent mesopores, this step being ended as soon as a predetermined minimum silicon wall thickness of the rib regions is reached, the uncovering of the rib regions, which are arranged at the end remote from the semiconductor substrate between adjacent mesopores. The method can be used to fabricate a vertical transistor and a memory cell having a select transistor of this type.