Method of fabricating SOI wafer
US7084046B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2002 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Jan 20, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76254
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
After completion of annealing for bonding of the base wafer 1 and bond wafer 2, the bond wafer 2 is thinned to a first thickness suitable for ion implantation, and boron is ion-implanted to thereby form a high-boron-concentration layer 10. A second thinning step based on selective etching is then carried out while using the high-boron-concentration layer 10 as an etch stop layer. This is successful in providing a method of fabricating an SOI wafer which is suppressed both in intra-wafer uniformity of the firm thickness and in inter-wafer uniformity of the film thickness even when a required level for the thickness of the SOI layer is extremely small.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.