Bit line contact structure and fabrication method thereof
US7084057B2 · kind B2 · utility
0Cited by
2References
18Claims
0Family size
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Inventor
Key dates
| Filing date | Dec 21, 2004 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Dec 26, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bit line contact structure and fabrication method thereof. The method includes providing a substrate having a transistor, with a gate electrode, drain region, and source region, on the substrate, blanketly forming a first dielectric layer on the transistor using spin coating, and patterning the first dielectric layer, forming a via exposing the drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.