Method of forming different oxide thickness for high voltage transistor and memory cell tunnel dielectric
US7084453B2 · kind B2 · utility
4Cited by
35References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 19, 2004 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | May 19, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/981
Abstract
A semiconductor memory device and method for making the same, where a memory cell and high voltage MOS transistor are formed on the same substrate. An insulating layer is formed having a first portion that insulates the control and floating gates of the memory cell from each other, and a second portion that insulates the poly gate from the substrate in the MOS transistor. The insulating layer is formed so that its first portion has a smaller thickness than that of its second portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.