Shielded platform for die-bonding an analog die to an FPGA
US7084487B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 9, 2003 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Jan 20, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit die contains digital circuitry that emits noise (for example, in the audio frequency range) in the form of electromagnetic radiation. The integrated circuit die is provided with a shielded platform above the digital circuitry. The shielded platform has one metal plate that is coupled to an analog supply voltage source and another metal plate that is coupled to an analog ground terminal. The digital circuitry is coupled to a digital supply voltage source. A second die with noise-sensitive analog circuitry is stacked on the shielded platform and is shielded by the shielded platform from the noise. The analog circuitry is powered by the analog supply voltage source. Conductive vias in a predetermined pattern protrude through the shielded platform and provide a standardized way of connecting any one of numerous noise-sensitive second dice to the relatively noisy digital circuitry of the underlying die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.