Process and lead frame for making leadless semiconductor packages
US7087461B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2004 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Aug 11, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. Each lead of the lead frame has a first portion, a second portion and a third portion connecting the first portion and the second portion, wherein the first metal layer is not provided on the third portion. After a wire bonding step and an encapsulating step are conducted, a second metal layer is selectively plated on the first portions and the second portions of the leads and the die pads exposed from the bottom of the molded product. Then, the third portion of each lead is selectively etched away such that the first portion and the second portion are electrically isolated from each other. Finally, a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.