Method for controlling trench depth in shallow trench isolation features
US7087498B2 · kind B2 · utility
3Cited by
10References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2003 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Aug 4, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3085
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a trench in a semiconductor silicon substrate. An anti-reflective coating layer and a photoresist layer are formed over the substrate and patterned in accordance with a location for the trench. During the trench etch into the silicon substrate, the etch environment is monitored to detect the material of the anti-reflective coating layer. The etch process is controlled in response to detecting the removal of this material and the known etch rate differential between the anti-reflective coating material layer and the silicon substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.