Area efficient stacking of antifuses in semiconductor device
US7087975B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2000 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Dec 28, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is provided which is formed of a wafer having on a surface thereof an area efficient arrangement of at least two antifuses in vertically stacked relation and sharing a common intermediate electrode therebetween. The arrangement includes at least one lower antifuse having a lower counter electrode and a lower fusible insulator portion defining a lower fuse element of an initial high electrical resistance state which interconnects the lower counter electrode with the common intermediate electrode, and at least one upper antifuse, which may be the same as or different from the lower antifuse, the upper antifuse having an upper counter electrode and an upper fusible insulator portion defining an upper fuse element of an initial high electrical resistance state which interconnects the upper counter electrode with the common intermediate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.