Reducing power consumption during MRAM writes using multiple current levels
US7088608B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2003 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Jan 25, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reduced power method of writing MRAM bits is disclosed. The reduced power method includes writing MRAM bits by applying a first magnetic field having a low magnitude, then determining if the bit has switched. If not, a second magnetic field having a higher magnitude is applied. Applying magnetic fields to an MRAM bit cell is accomplished by sending a current pulse through a strip line adjacent to the MRAM bit cell. The technique can be performed for every write to an MRAM bit. Alternatively, the weaker magnetic field can be applied during system test or system initialization, and if the weaker field fails to write the bit to a desired value, the failing result is stored and each subsequent write to the MRAM bit utilizes the stronger magnetic field.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.