Method for design validation of complex IC
US7089517B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2001 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Apr 21, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for design validation of complex IC with use of a combination of electronic design automation (EDA) tools and a design test station at high speed and low cost. The EDA tools and device simulator are linked to the event based test system to execute the original design simulation vectors and testbench and make modifications in the testbench and event based test vectors until satisfactory results are obtained. The event based test vectors are test vectors in an event format in which an event is any change in a signal which is described by its timing and the event based test system is a test system for testing an IC by utilizing the event based test vectors. Because EDA tools are linked with the event based test system, these modifications are captured to generate a final testbench that provides satisfactory results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.