Process flow for a performance enhanced MOSFET with self-aligned, recessed channel

US7091092B2 · kind B2 · utility

Assignees

• Chartered Semiconductor Manufacturing LTD · SG
• NATIONAL UNIVERSITY OF SINGAPORE · SG

Inventors

• Sneedharan Pillai Sneelal · Thiruvananthapuram, IN
• Francis Poh · Singapore, SG
• James Yong Meng Lee · Singapore, SG
• Alex See · Singapore, SG
• C. K. Lau · Singapore, SG
• Ganesh Samudra · Singapore, SG

Key dates

• Filing date: Feb 5, 2002
• Grant date: Aug 15, 2006
• Expiry date: Feb 17, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017

Abstract

A method for forming a self-aligned, recessed channel, MOSFET device that alleviates problems due to short channel and hot carrier effects while reducing inter-electrode capacitance is described. A thin pad oxide layer is grown overlying the substrate and a gate recess, followed by deposition of a thick silicon nitride layer filling the gate recess. The top surface is planarized exposing the pad oxide layer. An additional oxide layer is grown, thickening the pad oxide layer. A portion of the silicon nitride layer is etched away and additional oxide layer is again grown. This forms a tapered oxide layer along the sidewalls of the gate recess. The remaining silicon nitride layer is removed. The oxide layer at the bottom of the gate recess is removed and a gate dielectric layer is grown. Gate polysilicon is deposited filling the gate recess. S/D implantations, metallization, and passivation complete fabrication of the device.