Method and structure to decrease area capacitance within a buried insulator device
US7091560B2 · kind B2 · utility
1Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2004 |
| Grant date | Aug 15, 2006 |
| Priority date | — |
| Expiry date | Aug 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6758
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Method and structure to decrease area capacitance within a buried insulator device structure are disclosed. A portion of the substrate layer of a buried insulator structure opposite the insulator layer from the gate is doped with the same doping polarity as the source and drain regions of the device, to provide reduced area capacitance. Such doping may be limited to portions of the substrate which are not below the gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.