Apparatus and method for managing voltage buses
US7096304B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2003 |
| Grant date | Aug 22, 2006 |
| Priority date | — |
| Expiry date | Oct 17, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present technique relates to a method and apparatus for managing voltage buses. In a memory device, such as SRAM or DRAM, a periphery voltage bus may supply voltage to periphery circuitry and an array voltage bus may supply voltage to array circuitry. A bridge circuit may be utilized to isolate the buses from each other and couple the buses together, depending on the control signals are received by the bridge circuit. As such, the bridge circuit enhances the operation of the memory device by reducing duplicative circuits and equalizing the voltage that are applied to the buses. In addition, the bridge circuit isolates the buses from each other to protect sensitive circuitry in the array and periphery circuitry from noise on the other bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.