Switching to original modifiable instruction copy comparison check to validate prior translation when translated sub-area protection exception slows down operation
US7096460B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2003 |
| Grant date | Aug 22, 2006 |
| Priority date | — |
| Expiry date | Jun 16, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer system that translates target instructions from a target instruction set into host instructions from a host instruction set, a method for checking a sequence of target instructions for changes. The method includes testing whether the target instructions at a memory location have changed subsequent to the translating by examining a bit indicator associated with the memory location and determining whether the testing is slowing the operation of the computer system. If the testing is slowing the operation of the computer system, a checking process initiated, which includes storing a copy of the sequence of target instructions and comparing the copy with the sequence of target instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.