Methods for transistors formation using selective gate implantation
US7098098B2 · kind B2 · utility
1Cited by
11References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2002 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Sep 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/324
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted into the exposed gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.