Semiconductor device having optimized shallow junction geometries and method for fabrication thereof
US7098099B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2005 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Feb 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0184
Abstract
The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). In one embodiment, the method includes growing an oxide layer 120 from a substrate 104, 106 over a first dopant region 122 and a second dopant region 128, implanting a first dopant through the oxide layer 120, into the substrate 104 in the first dopant region 122, and adjacent a gate structure 114, and substantially removing the oxide layer 120 from the substrate within the second dopant region 128. Subsequent to the removal of the oxide layer 120 in the second dopant region 128, a second dopant that is opposite in type to the first dopant is implanted into the substrate 106 and within the second dopant region 128 and adjacent a gate structure 114.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.