Method of forming dual damascene structure
US7098130B1 · kind B1 · utility
3Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2004 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Dec 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76813
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming dual damascene features in a dielectric layer. Vias are partially etched in the dielectric layer. A trench pattern mask is formed over the dielectric layer. Trenches are partially etched in the dielectric layer. The trench pattern mask is stripped. The dielectric layer is further etched to complete etch the vias and the trenches in the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.