Method of etching ferroelectric devices
US7098142B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2003 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Apr 2, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of etching a ferroelectric device 100 having a ferroelectric layer 112 between a top and a bottom electrode 114, 108 is disclosed herein. Hardmasks 116, 118 are deposited on the top electrode 114, two or more hardmasks being spaced apart by narrow first regions 115 and spaced apart from other hardmasks by wider second regions 117. The top electrode 114 and ferroelectric layer 112 are then etched to pattern the top electrode 114 thus forming capacitors 102, 104, and the bottom electrode 108 is etched by a process in which the second regions are etched more slowly than the second regions. Those capacitors having a first region between them have a common bottom electrode 108, but in the second regions the bottom electrode is severed. To pattern the bottom electrode 108, a fluorine-based chemistry followed thereafter by a CO-based chemistry are used in a two step etching process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.