Centralizing the lock point of a synchronous circuit
US7098714B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 8, 2003 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Dec 13, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method to establish the lock point of a digital synchronous circuit (e.g., a DLL) at the center of or close to the center of its delay line is disclosed. The synchronous circuit is configured to selectively use either a reference clock or its inverted version as the clock signal input to the delay line based on a relationship among the phases of the reference clock, the inverted reference clock, and a feedback clock (generated at the output of the delay line). A delayed version of the feedback clock may be used during determination of the phase relationship. The selective use of the opposite phase of the reference clock for the input of the delay line results in centralization of the lock point for most cases as well as improvement in the tuning range and the time to establish the initial lock, without requiring an additional delay line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.