Nonvolatile flash memory and method of operating the same
US7099192B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2004 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Jun 7, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory and a method of operating the same are proposed. The nonvolatile memory has single-gate memory cells, wherein a structure of a transistor and a capacitor is embedded in a semiconductor substrate. The transistor comprises a first conducting gate stacked on the surface of a dielectric with doped regions formed at two sides thereof as a source and a drain. The capacitor comprises a doped region, a dielectric stacked thereon, and a second conducting gate. The conducting gates of the capacitor and the transistor are electrically connected together to form a single floating gate of the memory cell. The semiconductor substrate is p-type or n-type. Besides, a back-bias program write-in and related erase and readout operation ways are proposed for the single-gate memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.