Error recovery for nonvolatile memory
US7099194B2 · kind B2 · utility
129Cited by
22References
9Claims
0Family size
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Key dates
| Filing date | Dec 3, 2004 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Dec 3, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An error recovery technique is used on marginal nonvolatile memory cells. A marginal memory cell is unreadable because it has a voltage threshold (VT) of less than zero volts. By biasing adjacent memory cells, this will shift the voltage threshold of the marginal memory cells, so that it is a positive value. Then the VT of the marginal memory cell can be determined. The technique is applicable to both binary and multistate memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.