Flexible channel bonding and clock correction operations on a multi-block data path
US7099426B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2002 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Nov 5, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An elastic buffer for buffering a stream of data blocks includes a controller and a memory space, wherein multiple data blocks can be written and read during a single write or read clock cycle, respectively. Multiple read addresses are used for each read operation, allowing read access to non-contiguous memory locations during a single read cycle when desired. Therefore, the elastic buffer can perform clock correction and channel bonding operations on data streams that include correction and alignment data block sequences that do not match the width of the memory space. A stagger bit can be used to indicate the timing of read address adjustments during clock correction and channel bonding operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.