Low cost source drain elevation through poly amorphizing implant technology
US7101743B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2004 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Jan 12, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/259
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming elevated source/drain regions. A gate structure is formed over a substrate. The substrate comprised of silicon. We form a polysilicon layer preferably using PVD or CVD over the gate structure and the substrate. A poly/Si interface is formed between the polysilicon layer and the substrate. We perform a poly/Si interface amorphization implant to amorphize at least the poly/Si interface in the S/D areas and to from an amorphous region. We anneal the substrate to crystallize the amorphous region and the polysilicon layer over the amorphous region to form an elevated silicon region in the source/drain area. Next, source/drain regions in are formed in the elevated silicon regions and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.