Testing logic and embedded memory in parallel
US7103814B2 · kind B2 · utility
8Cited by
19References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2002 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Jan 1, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technique to perform logic and embedded memory tests using logic scan chain testing procedures in parallel with memory built in self test (BIST). This is accomplished with a combination of voltage isolation between memory and logic segments, and isolation between logic and memory test clocks. A test algorithm is introduced to enable and disable the scan chain operation during BIST operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.