Method and system for reducing test data volume in the testing of logic products

US7103816B2 · kind B2 · utility

Assignee

• Cadence Design Systems, Inc. · US

Inventors

• Frank Distler · Williston, US
• Leonard O. Farnsworth, III · Middlebury, US
• Andrew Ferko · Waterbury, US
• Brion Keller · Binghamton, US
• Bernd Koenemann · San Jose, US
• Donald L. Wheater · South Burlington, US

Key dates

• Filing date: Jan 23, 2001
• Grant date: Sep 5, 2006
• Expiry date: Sep 23, 2021

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/31921
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method and system for reducing test data volume in the testing of logic products such as integrated circuit chips. Test data loaded by a tester into the logic product to apply to portions of combinational logic circuitry therein in order to detect faults comprises “care” bits and “non-care” bits. The care bits target focal faults of interest in the logic circuitry being tested while the non-care bits do not. According to the invention, non-care bits in the test vector data are filled with repetitive background data to provide for a high degree of compressibility of the test vector data. A substantial portion of the care bits may also be set to a repetitive value and the original values later recovered.