Process and apparatus for placement of megacells in ICs design
US7103865B2 · kind B2 · utility
2Cited by
13References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2003 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | May 9, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An IC layout containing megacells placed in violation of design rules is corrected to remove design rule violations while maintaining the original placement as near as practical. The sizes of at least some of the megacells are inflated. The megacells are placed and moved in a footprint of the circuit in a manner to reduce placement complexity. The placement of the megacells is permuted to reduce placement complexity. Additional movements are be applied to the permuted placement to further reduce placement complexity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.