Method of inhibiting metal silicide encroachment in a transistor
US7105429B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 10, 2004 |
| Grant date | Sep 12, 2006 |
| Priority date | — |
| Expiry date | Mar 3, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/321
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method inhibits metal silicide encroachment in channel regions in a transistor that uses metal silicide as an electrical contact to its terminals. A metal layer is deposited overlying the transistor. A first anneal that is a low temperature anneal forms metal silicide regions to source, gate and drain terminals of the transistor. The low temperature inhibits lateral encroachment. Unsilicided portions of the metal are removed and followed by an ion implant of an element, such as nitrogen, that diffuses into the metal silicide regions. A second anneal at a higher temperature than the first anneal is completed wherein the implanted nitrogen ions prevent lateral encroachment of metal silicide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.