Dharmesh Jawarani
18Patents
8h-index
25Co-inventors
64Inventor score
Filing activity: Nov 21, 2003 → Sep 21, 2011
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7749884B2 | Method of forming an electronic device using a separation-enhancing species | Emerging Cross-Sectional Technologies | 258 | Active |
| US7521314B2 | Method for selective removal of a layer | Electricity | 28 | Active |
| US7235473B2 | Dual silicide semiconductor fabrication process | Electricity | 11 | Expired |
| US8043888B2 | Phase change memory cell with heater and method therefor | Physics | 10 | Active |
| US7544576B2 | Diffusion barrier for nickel silicides in a semiconductor fabrication process | Electricity | 10 | Active |
| US7105429B2 | Method of inhibiting metal silicide encroachment in a transistor | Electricity | 9 | Expired |
| US7544575B2 | Dual metal silicide scheme using a dual spacer process | Electricity | 9 | Active |
| US7262105B2 | Semiconductor device with silicided source/drains | Electricity | 8 | Expired |
| US7235471B2 | Method for forming a semiconductor device having a silicide layer | Electricity | 5 | Expired |
| US7510922B2 | Spacer T-gate structure for CoSi2 extendibility | Electricity | 4 | Expired |
| US7713801B2 | Method of making a semiconductor structure utilizing spacer removal and semiconductor structure | Electricity | 3 | Active |
| US7927934B2 | SOI semiconductor device with body contact and method thereof | Electricity | 3 | Active |
| US8076215B2 | Method of forming an electronic device using a separation technique | Emerging Cross-Sectional Technologies | 2 | Active |
| US8247850B2 | Dual interlayer dielectric stressor integration with a sacrificial underlayer film stack | Electricity | 2 | Active |
| US7622339B2 | EPI T-gate structure for CoSi2 extendibility | Electricity | 1 | Active |
| US7998822B2 | Semiconductor fabrication process including silicide stringer removal processing | Electricity | 1 | Active |
| US8575588B2 | Phase change memory cell with heater and method therefor | Physics | 1 | Active |
| US7446006B2 | Semiconductor fabrication process including silicide stringer removal processing | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.