Heterojunction tunneling diodes and process for fabricating same
US7105866B2 · kind B2 · utility
17Cited by
568References
8Claims
0Family size
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Key dates
| Filing date | Aug 5, 2004 |
| Grant date | Sep 12, 2006 |
| Priority date | — |
| Expiry date | Aug 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/08
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.