Process sequence for doped silicon fill of deep trenches
US7109097B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2004 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Dec 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/047
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.