Apparatus and method for renaming a data block within a cache
US7111125B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 2, 2003 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Dec 29, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor apparatus is provided that enables exclusive allocation and renaming of a block of cache lines. The apparatus includes translation logic and execution logic. The translation logic translates a block allocate and rename instruction into a micro instruction sequence that directs a microprocessor to allocate a first block of cache lines in an exclusive state and to copy the contents of a second block of cache lines into the first block of cache lines. The execution logic is coupled to the translation logic. The execution logic receives the micro instruction sequence, and issues transactions over a memory bus that requests the first block of cache lines in the exclusive state. Upon granting of exclusive rights, the execution logic copies the contents of the second block of cache lines into the first block of cache lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.