Test pattern compression for an integrated circuit test environment
US7111209B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Jan 31, 2003 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | May 31, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318547
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.