Circuits and methods for testing programmable logic devices using lookup tables and carry chains
US7111214B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2002 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | May 12, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuit implementations and test methods enable the testing of lookup table (LUT) input paths, “stuck at” memory cell values, and carry chains. One method includes storing a first bit pattern in each LUT, configuring the carry chain to perform a wide AND function of the LUT outputs, and cycling the inputs of each LUT while comparing the carry chain output to an expected value and reporting the PLD faulty if a difference is detected. The carry chain is configured to perform a wide OR function, and the cycling step is repeated. The bit pattern within each LUT is changed to the complement of the first bit pattern by providing a series of shift commands or by otherwise storing new values in the LUT, and the configuring and cycling steps are repeated. The invention also provides PLD circuit implementations that can be used to perform the described methods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.