Methods of reducing the susceptibility of PLD designs to single event upsets
US7111215B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2004 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Apr 3, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17764
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods of implementing designs in programmable logic devices (PLDs) to reduce susceptibility to single-event upsets (SEUs) by taking advantage of the fact that most PLD designs leave many routing resources unused. The unused routing resources can be used to provide duplicate routing paths between source and destination of signals in the design. The duplicate paths are selected such that an SEU affecting one of the duplicate paths simply switches the signal between the two paths. Thus, if one path is disabled due to an SEU, the other path can still provide the necessary connection, and the functionality of the design is unaffected. The methods can be applied, for example, to routing software for field programmable gate arrays (FPGAs) having programmable routing multiplexers controlled by static RAM-based configuration memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.