Source lines for NAND memory devices
US7112488B2 · kind B2 · utility
22Cited by
3References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 27, 2004 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | May 27, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are provided. A NAND memory device has a source line connected to two or more columns of serially-connected floating-gate transistors. The source line includes a first conductive layer formed on a substrate and coupled to source select gates associated with the two or more columns of serially-connected floating-gate transistors. The source line also includes a second conductive layer formed on the first conductive layer, where the second layer has a greater electrical conductivity than the first conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.