Sub-micron space liner and densification process
US7112513B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2004 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | Jul 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a spin-on dielectric (SOD) material. A densification process is then applied, whereby the SOD material contracts and the oxidizable liner expands. Preferably, the temperature is ramped up while oxidizing during at least part of the densification process. The resulting trench has a negligible vertical wet etch rate gradient and a negligible recess at the top of the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.