John Smythe
139Patents
15h-index
71Co-inventors
89Inventor score
Filing activity: Nov 3, 1997 → Sep 18, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9865456B1 | Methods of forming silicon nitride by atomic layer deposition and methods of forming semiconductor structures | Electricity | 379 | Active |
| US7521378B2 | Low temperature process for polysilazane oxidation/densification | Electricity | 133 | Expired |
| US6165846A | Method of eliminating gate leakage in nitrogen annealed oxides | Electricity | 71 | Expired |
| US6190973A | Method of fabricating a high quality thin oxide | Electricity | 67 | Expired |
| US8223539B2 | GCIB-treated resistive device | Electricity | 58 | Active |
| US8048755B2 | Resistive memory and methods of processing resistive memory | Electricity | 53 | Active |
| US7514366B2 | Methods for forming shallow trench isolation | Electricity | 36 | Active |
| US8114468B2 | Methods of forming a non-volatile resistive oxide memory array | Emerging Cross-Sectional Technologies | 31 | Active |
| US7112513B2 | Sub-micron space liner and densification process | Electricity | 23 | Expired |
| US7785978B2 | Method of forming memory cell using gas cluster ion beams | Electricity | 23 | Active |
| US7737039B2 | Spacer process for on pitch contacts and related structures | Emerging Cross-Sectional Technologies | 18 | Active |
| US9985049B1 | Arrays of elevationally-extending strings of memory cells and methods of forming memory arrays | Electricity | 17 | Active |
| US6642112B1 | Non-oxidizing spacer densification method for manufacturing semiconductor devices | Electricity | 17 | Expired |
| US7439157B2 | Isolation trenches for memory devices | Electricity | 16 | Active |
| US7851307B2 | Method of forming complex oxide nanodots for a charge trap | Electricity | 15 | Active |
| US7271463B2 | Trench insulation structures including an oxide liner that is thinner along the walls of the trench than along the base | Electricity | 15 | Expired |
| US7557420B2 | Low temperature process for polysilazane oxidation/densification | Electricity | 14 | Expired |
| US8241944B2 | Resistive RAM devices and methods | Electricity | 14 | Active |
| US8409915B2 | Methods of forming memory cells | Electricity | 14 | Active |
| US8598560B1 | Resistive memory elements exhibiting increased interfacial adhesion strength, methods of forming the same, and related resistive memory cells and memory devices | Electricity | 13 | Active |
| US8034655B2 | Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming non-volatile resistive oxide memory cells and memory arrays | Physics | 13 | Active |
| US7271464B2 | Liner for shallow trench isolation | Electricity | 12 | Expired |
| US8735211B2 | Resistive RAM devices and methods | Electricity | 12 | Active |
| US8211803B2 | Spacer process for on pitch contacts and related structures | Emerging Cross-Sectional Technologies | 11 | Active |
| US8129289B2 | Method to deposit conformal low temperature SiO2 | Electricity | 9 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.