Process for forming a dual damascene structure
US7112532B2 · kind B2 · utility
4Cited by
16References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2003 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | Dec 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76813
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention describes a method for forming a dual damascene structure. An etch stop layer (150) is formed on a dielectric layer (140). A second dielectric layer (160) is formed on the etch stop layer (150) and an ARC layer (170) is formed the second dielectric layer. A first trench (185) and a second trench (195) are then simultaneously formed in the first and second dielectric layers (140) and (160) respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.