Field effect transistor with electroplated metal gate
US7112851B2 · kind B2 · utility
30Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2005 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | Oct 26, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/667
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.