Integrated getter area for wafer level encapsulated microelectromechanical systems
US7115436B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2004 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | Mar 17, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/48091
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
There are many inventions described and illustrated herein. In one aspect, present invention is directed to a thin film encapsulated MEMS, and technique of fabricating or manufacturing a thin film encapsulated MEMS including an integrated getter area and/or an increased chamber volume, which causes little to no increase in overall dimension(s) from the perspective of the mechanical structure and chamber. The integrated getter area is disposed within the chamber and is capable of (i) “capturing” impurities, atoms and/or molecules that are out-gassed from surrounding materials and/or (ii) reducing and/or minimizing the adverse impact of such impurities, atoms and/or molecules (for example, reducing the probability of adding mass to a resonator which would thereby change the resonator's frequency). In this way, the thin film wafer level packaged MEMS of the present invention includes a relatively stable, controlled pressure environment within the chamber to provide, for example, a more stable predetermined, desired and/or selected mechanical damping of the mechanical structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.