Method for fabricating an integrated circuit device with through-plating elements and terminal units

US7115501B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Uwe Kahler · Dresden, DE
• Dirk Offenberg · Dresden, DE

Key dates

• Filing date: Sep 10, 2004
• Grant date: Oct 3, 2006
• Expiry date: Apr 2, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76877
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for fabricating an integrated circuit device, an electrically conductive substrate being provided, an insulation layer being deposited on the substrate, the insulation layer being etched in structures, a contact-making layer being deposited on the patterned insulation layer and on the substrate in depressions which have first and second lateral dimensions, the contact-making layer being etched back in such a way that the contact-making layer is preserved in the structures with the depressions which have first lateral dimensions of the order of magnitude of the structure depth of the insulation layer and the contact-making layer is removed in the structures with depressions which have second lateral dimensions significantly greater than the structure depth of the insulation layer.