Semiconductor circuit configuration and semiconductor memory device
US7115897B2 · kind B2 · utility
2Cited by
3References
57Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2003 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | Apr 9, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor circuit configuration has at least one pair of complementary operating field-effect transistors in which each transistor has a gate region, first and second source/drain regions and also a channel region with or made of an organic semiconductor material that is provided in between. It is furthermore provided that the gate regions are formed such that they are electrically coupled to one another via a capacitor configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.