Strained silicon fin structure

US7115945B2 · kind B2 · utility

Assignee

• Sharp Laboratories of America, Inc. · US

Inventors

• Jong-Jan Lee · Camas, US
• Sheng Teng Hsu · Camas, US
• Douglas J. Tweet · Camas, US
• Jer-Shen Maa · Vancouver, US

Key dates

• Filing date: Jan 6, 2006
• Grant date: Oct 3, 2006
• Expiry date: Jan 6, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/751

Abstract

Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing short channel effect and enhancing drive current. The silicon fin channel of the disclosed finFET device is a strained silicon fin channel, comprising a strained silicon layer deposited on a seed fin having different lattice constant, for example, a silicon layer deposited on a silicon germanium seed fin, or a carbon doped silicon layer deposited on a silicon seed fin. The lattice mismatch between the silicon layer and the seed fin generates the strained silicon fin channel in the disclosed finFET device to improve hole and electron mobility enhancement, in addition to short channel effect reduction characteristic inherently in a finFET device.