Method and circuit of plasma damage protection
US7116606B2 · kind B2 · utility
5Cited by
8References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2005 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | Jan 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
A protection circuit to discharge plasma-induced charges in a semiconductor device or integrated circuit includes a PMOS transistor and a diode. The PMOS transistor includes a substrate, a drain, a source, and a gate, the source being coupled to receive the plasma-induced charges. The diode has a positive terminal coupled to the substrate of the PMOS transistor and a negative terminal coupled the gate of the PMOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.