Methods for optimizing package and silicon co-design of integrated circuit
US7117467B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2004 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | Feb 13, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to methods for optimizing package and silicon co-design of an integrated circuit. A composite bump pattern for an integrated circuit is created based on a first library including at least one bump pattern template. PCB and Die constraints of the integrated circuit are then reviewed. A partial package design for the integrated circuit is generated based on a second library including at least one partial package template. A partial silicon design for said integrated circuit is started. A full package design for the integrated circuit is then completed. A full silicon design for the integrated circuit is completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.