Methods of fabricating silicon carbide devices with hybrid well regions
US7118970B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2004 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Jan 12, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/931
Abstract
MOS channel devices and methods of fabricating such devices having a hybrid channel are provided. Exemplary devices include vertical power MOSFETs that include a hybrid well region of silicon carbide and methods of fabricating such devices are provided. The hybrid well region may include an implanted p-type silicon carbide well portion in a p-type silicon carbide epitaxial layer, an implanted p-type silicon carbide contact portion that contacts the implanted p-type silicon carbide well portion and extends to a surface of the p-type epitaxial layer and/or an epitaxial p-type silicon carbide portion, at least a portion of the epitaxial p-type silicon carbide well portion corresponding to a p-type channel region of the MOSFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.