Method and structure for a self-aligned silicided word line and polysilicon plug during the formation of a semiconductor device
US7119024B2 · kind B2 · utility
4Cited by
17References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2003 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Jan 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method used to form a semiconductor device provides a silicide layer on a plurality of transistor word lines and on a plurality of conductive plugs. In one embodiment, the word lines, one or more sacrificial dielectric layers on the word lines, conductive plugs, and a conductive enhancement layer are formed through the use of a single mask. An in-process semiconductor device which can be formed using one embodiment of the inventive method is also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.