NROM device
US7119396B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2004 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Dec 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/018
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a memory device (and the resulting device) by forming an electron trapping dielectric material over a substrate, forming conductive material over the dielectric material, forming a spacer of material over the conductive material, removing portions of the dielectric material and the conductive material to form segments thereof disposed underneath the spacer of material, forming first and second spaced-apart regions in the substrate having a second conductivity type different from that of the substrate, with a channel region extending between the first and second regions, with the segments of the dielectric and first conductive materials being disposed over a first portion of the channel region for controlling a conductivity thereof, and forming a second conductive material over and insulated from a second portion of the channel region for controlling a conductivity thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.