Memory transaction ordering
US7120765B2 · kind B2 · utility
17Cited by
17References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2002 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Dec 31, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1626
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Machine-readable media, methods, and apparatus are described which order memory transactions to increase utilization of multiple memory channels. In some embodiments, a processor may determine an issue order for memory transactions based on the memory channels that are to service the memory transactions. In some embodiments, the processor attempts to obtain an issue order that minimizes or reduces the number of idle periods experienced by the memory channels. Further, the processor may issue the memory transactions to an external memory controller for servicing in the determined issue order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.